1. Field of the Invention
The present invention relates to testing of integrated circuits, and more specifically to a method and apparatus for controlling the content of specific desired memory elements when testing integrated circuits using a sequential scanning technique such as Automatic Test Pattern Generation (ATPG).
2. Related Art
Integrated circuits are often tested to verify whether the circuits operate in a desired manner. For example, an integrated circuit may be tested to ensure that each component (within the integrated circuit) generates a desired output in response to corresponding inputs, and such testing is often referred to as functional testing.
Similarly, the delays in various paths of an integrated circuit may be measured to ensure that the paths generate the respective outputs within any time limits as may be necessary for the operation of the integrated circuit at a desired clock frequency, and such testing is often referred to as delay testing.
Sequential scanning techniques are often employed to test integrated circuits. As is well known in the relevant arts, Automatic Test Pattern Generation (ATPG) is an example of such a sequential scanning approach. In a typical scenario, the memory elements (e.g., flip-flops) are connected in sequence, and a desired sequence of bits (“test pattern”) is sequentially scanned into the memory elements. The circuit is said to be in a ‘initialization mode’ when a test pattern is being scanned into the memory elements of the circuit.
An integrated circuit may be switched from the initialization mode to an evaluation mode (referred to as “functional mode” in the relevant arts), and the results generated by various combinatorial logic elements (based on the scanned test pattern) may be stored in the corresponding memory elements. The generated outputs may be examined and the delays in various paths may be measured to verify whether the integrated circuit operates in a desired manner.
It is often desirable to control the content of specific desired memory elements while testing integrated circuits. For example, it may be desirable to use one value for a subject memory element in one time instance of the evaluation mode and another value for the subject memory element in the next time instance, while leaving the content of remaining memory elements unchanged.
Use of such a different value may be desirable, for example, to excite (cause transition along) a specific path of the integrated circuit. Various timing parameters and logic functional operation (e.g., absence of stuck-at condition) may be measured/verified by using such tests. By changing only one bit, and not others which may effect a transition anywhere in a subject path, it may be ensured that the transition is caused only by a memory element connected at one end of the subject path. Accordingly, it may be desirable to control the content of memory elements.
Several prior approaches have been used to control the content of desired memory elements. As an illustration, with reference to the example of previous paragraph, the memory elements are connected in such a sequence that all the memory elements storing one logical value are connected in one direction of the subject memory element, and memory elements with another value are connected in the another direction.
Thus, the test pattern may merely need to be shifted by one position to shift-in a desired bit value into the specific memory element without effectively changing the value in the other memory elements. One problem with such an approach is that the approach imposes (or requires) a specific order in which the memory elements are to be connected, and the corresponding connectivity requirement may pose challenges in layout and routing while designing an integrated circuit. In addition, different tests may require conflicting paths Accordingly, the approach may not be suitable for at least some environments.
In another approach, additional memory element (“dummy memory elements”) may be used in the middle of sequence of memory elements, for example, to avoid undesirable changes in values. As an illustration, it is assumed that a transition is desirable in one (“subject memory element”) of the sequence of memory elements and such a transition can be attained by a shift operation. Assuming further that such a shift would shift-in a undesired value from the subject memory element to an adjacent memory element, a dummy memory element may be used in between the two elements. The dummy element can be pre-set to a value to ensure that the shift operation does not result in an undesired value in the adjacent memory element.
However, one disadvantage of such an approach is that a large number of memory elements may be required to support, for example, excitation of various paths, and the resulting consumption of space (on the integrated circuit) and power consumption may be unacceptable. Accordingly, what is needed is a method apparatus which enables the content of specific memory elements to be controlled when testing integrated circuits using sequential scanning techniques such as ATPG.